Programming Systolic Arrays Richard
نویسنده
چکیده
This paper presents the New Systolic Language as a general solution to the problem systolic programming. The language provides a simple programming interface for systolic algorithms suitable for di erent hardware platforms and software simulators. The New Systolic Language hides the details and potential hazards of inter-processor communication, allowing data ow only via abstract systolic data streams. Data ows and systolic cell programs for the co-processor are integrated with host functions, enabling a single le to specify a complete systolic program.
منابع مشابه
Programming Systolic Arrays
This paper presents the New Systolic Language as a general solution to the problem systolic programming. The language provides a simple programming interface for systolic algorithms suitable for diierent hardware platforms and software simulators. The New Systolic Language hides the details and potential hazards of inter-processor communication, allowing data ow only via abstract systolic data ...
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We offer a methodology for simplifying the design and analysis of systolic systems. Speciflcally, we give characterizations of systolic arrays in terms of (single processor) sequential machines which are easier t o analyze and to program. We give several examples to illustrate the design methodology. In particular, we show how systolic arrays can be easily designed to implement priority queues,...
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This paper introduces new type of m-ary systolic arrays called m-ary reversible systolic arrays which extends the new concept of two-valued reversible systolic arrays that was introduced in the first part of my article. The m-ary quantum systolic architectures’ computations of the new type of systolic arrays are also introduced. The new m-ary systolic arrays maintain the high level of regularit...
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New type of systolic arrays called reversible systolic arrays is introduced. The two-valued quantum systolic architectures’ realizations and computations of the new systolic arrays are also introduced. It is shown that the new systolic arrays maintain the high level of regularity while exhibiting the new fundamental bijectivity (reversibility) and quantum superposition properties. A systolic ar...
متن کامل991 International Conference on Parallel Processing B-sys: a 470-processor Programmable Systolic Array
This paper presents an architecture for programmable systolic arrays that provides simple and eecient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.
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تاریخ انتشار 1991